The state of the art programming of a ferroelectric memory transistor requires application of a voltage to a control gate, thus pulling the ferroelectric thin film to saturation, polarizing to both polarities. When holes are pulled to the top of the memory film, the threshold voltage of an n-channel memory transistor is programmed to a high threshold voltage state. When electrons are pulled to the top of the memory film, the threshold voltage of the n-channel memory transistor is programmed to a low-threshold voltage state. In order to minimize standby power consumption, the threshold voltage of the n-channel memory transistor must be a positive voltage in its standby condition. Therefore, the intrinsic threshold voltage of the n-channel memory transistor has to be larger than one-half of the memory window of the device, requiring that the channel doping density be very large, which results in a low effective channel mobility. The forgoing conditions result in a degraded memory operation speed. A large polarization of a MFMIS transistor also induces a large depolarization field, resulting in a relatively short memory retention time.
For an n-channel metal-ferroelectric metal oxide (MFMox) memory transistor, the metal oxide is a n-type semiconductive thin film deposited onto a p-type silicon (well). When the device is programmed to its “OFF” state, i.e., a high threshold voltage state, the ferroelectric thin film is polarized, with the holes therein pulled to the interface with the top electrode. The n-type semiconductive metal oxide is depleted and the surface of the p-type silicon is accumulated. When the gate electrode is grounded, the voltage across the ferroelectric thin film generates a voltage of a polarity opposite that of the polarization voltage. As a result, the polarization charge decreases with time. The voltage across the ferroelectric is called the de-polarization voltage. The de-polarization field tends to decrease the “OFF” state threshold voltage.
When a memory device is programmed to a low threshold voltage, the ferroelectric thin film is polarized with negative charges pulled to the top of the FE-electrode interface. The n-type semiconductive metal oxide is also completely depleted because of the flat band voltage of the gate stack and the metal oxide-to-p-type silicon induced depletion region. The flat band voltage is the difference of work function between the top electrode and the silicon substrate. Again, there is a de-polarization voltage across the ferroelectric thin film. The de-polarization thin film tends to increase the “ON” state threshold voltage. As the “ON” state threshold voltage is increased, the drive current of the memory transistor decreases and the speed of the device decreases. If the ferroelectric thin film is not polarized at the “ON” state, the “ON” state threshold voltage will not change with time, rendering device performance independent of time. There is no performance degradation. This is a significant advantage of an asymmetrical programming ferroelectric memory transistor.
U.S. Pat. No. 5,962,884, for Single Transistor Ferroelectric Memory Cell with Asymmetric Ferroelectric Polarization and Method for Same, of Hsu et al., granted Oct. 5, 1999, describes a method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate having plural conductive channels of a known doping type for use as a source junction region and a drain junction region; and depositing an FEM gate unit over the gate junction, wherein an insulating layer overlays the junction regions, the FEM gate unit and the substrate.
U.S. Pat. No. 6,048,740, for Ferroelectric Nonvolatile Transistor and Method of Making Same, of Hsu et al., granted Apr. 11, 2000, describes a method of fabricating a ferroelectric memory transistor using a lithographic process having a fine alignment tolerance which is equal to the alignment tolerance of the lithographic process.
U.S. Pat. No. 6,117,691, for Method of Making a Single Transistor Ferroelectric Memory Cell with Asymmetrical Ferroelectric Polarization, of Hsu et al., granted Sep. 12, 2000, describes a ferroelectric memory cell formed on a silicon substrate, wherein a FEM gate unit overlays the conductive channel of the gate junction region and an insulating layer overlays the junction regions, the FEM gate unit and the substrate.
U.S. Pat. No. 6,531,324, for MFOS Memory Transistor and Method of Fabricating Same, of Hsu et al., granted Mar. 11, 2003, describes a ferroelectric transistor gate structure with a ferroelectric gate and passivation sidewalls. The passivation sidewalls serve as insulators to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing passivation insulator material, etching the passivation insulator material using anisotropic plasma etching to form passivation sidewalls, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.
U.S. patent application Ser. No. 10/659,547, filed Sep. 9, 2003, for Conductive Metal Oxide Gate Ferroelectric Memory Transistor, of Hsu et al., describes a method of fabricating a ferroelectric device wherein a gate insulator is replaced with a conductive metal oxide.